To address the increasing demands of device scaling, new materials are being introduced into conventional Si CMOS processing at an unprecedented rate. Presentations collected here focus on understanding, from a chemistry and materials perspective, the mechanism of interface formation and defects at interfaces, for both conventional Si and alternative channel (Ge or III-V) systems. Several papers address reliability concerns for high-k/metal gate (basic physical models, charge trapping, etc.), while others cover characterization of the thin films and interfaces which comprise the gate stack. Topics include: advanced Si-based gate stacks; and alternate channel materials.