An embedded system is loosely defined as any system that utilizes electronics but is not perceived or used as a general-purpose computer. Usually, one or more electronic circuits or microprocessors are literally embedded in the system, either taking up roles that used to be performed by mechanical devices, or providing functionality that is not otherwise possible. The goal of this book is to investigate how formal methods can be applied to the domain of embedded system design. The emphasis is on the specification, representation, validation, and design exploration of such systems from a high-level perspective. The authors review the framework upon which the theories and experiments are based, and through which the formal methods are linked to synthesis and simulation. A formal verification methodology is formulated to verify general properties of the designs and demonstrate that this methodology is efficient in dealing with the problem of complexity and effective in finding bugs. However, manual intervention in the form of abstraction selection and separation of timing and functionality is required.
It is conjectured that, for specific properties, efficient algorithms exist for completely automatic formal validations of systems. This book presents a formal approach to high-level equivalence analysis, opening design exploration avenues that offer new possibilities. It is a work that can stand alone but at the same time is compatible with synthesis and simulation frameworks.