This work is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips.
The text is organized in 11 chapters as follows: chapter one provides an overview to the design of clock networks; chapter two specifies the timing requirements in digital design; chapter two shows the circuits of sequential elements including latches and flip-flops; chapter four describes the domino circuits, which need special clock signals; chapter five discusses the phase-locked loop (PLL) and delay-locked loop (DLL), which provide the clock generation and de-skewing for the on-chip clock distribution; chapter 6 summarizes the clock distribution techniques published in the state-of-the-art microprocessor chips; chapter 7 describes the CAD flow on the clock network simulation; chapter 8 gives the research work on low-voltage swing clock distribution; chapter 9 explores the possibility of placing the global clock tree on the package layers; chapter 10 shows the algorithms of balanced clock routing and wire sizing for the skew minimization; and chapter 11 shows a commercial CAD tool that deals with clock tree synthesis in the ASIC design flow.